A key objective in designing power MOSFETs is to reduce the on-resistance, i.e., the resistance of the MOSFET when it is turned on, to as low a value as possible. One way to achieve this objective is to reduce the channel resistance by increasing the cell density of the device. This increases the total cell perimeter and thereby provides a greater total gate width through which the current flows. Another way is to improve the transconductance of the active transistor portion of each cell by creating greater electrostatic coupling between the gate and the silicon which makes up the channel region of the device. This can be done be decreasing the thickness of the gate oxide layer (the layer, typically silicon dioxide, that separates the gate from the channel), which provides a lower threshold voltage and improved electrostatic coupling between the gate and the channel.
The gate oxide cannot be thinned without limit, however, because making the gate oxide thinner reduces the maximum gate voltage that can be applied to the device without rupturing the gate oxide and permanently destroying the MOSFET. It is difficult to design gate drive circuitry whose output is regulated within strict limits, and furthermore many circuits are subject to certain fault conditions (e.g., voltage spikes arising from transient conditions) that occasionally subject the gate to much higher than normal operating voltages. These conditions require the designer to thicken the gate oxide layer. In essence, the normal performance of the device is significantly compromised to protect against rare occurrences.
Thus there is a clear need for ways of safely reducing the thickness of the gate oxide layer and increasing the cell density of power MOSFET.